1. Field of the Invention
The present invention relates to semiconductor devices internally including voltage converting circuitry for converting an externally applied power supply voltage to produce an internal operating power supply voltage, and more particularly to a semiconductor memory device having on-chip internal down-converting circuitry for down-converting an external power supply voltage to produce an internal power supply voltage.
2. Description of the Background Art
With higher integration degree of semiconductor devices, transistor elements as the components thereof have been increasingly miniaturized. In order to ensure the reliability of such miniaturized transistor devices and to reduce charge/discharge current on signal lines with a signal amplitude being reduced and thus reduce current consumption, an on-chip voltage converting circuit for lowering an external power supply voltage is sometimes provided to drive internal circuitry with a voltage lower than the external power supply voltage produced by this voltage converting circuit.
The semiconductor devices having such a voltage converting circuit typically include a dynamic random access memory (DRAM). In the case of the DRAM, it is desirable to reduce an operating power supply voltage as much as possible in terms of high-speed operation thereof, device reliability and lower current consumption. However, since a logic gates of a processor for determining a system power supply voltage or the like are lower in integration degree than the DRAM, a power supply voltage of the logic cannot be reduced so low as the operating power supply voltage of the DRAM. In addition, the DRAM must maintain compatibility with the previous generations. Therefore, a higher system power supply voltage is down-converted within the DRAM to produce an internal operating power supply voltage lower than the system power supply voltage, thereby driving internal circuitry of the DRAM.
FIG. 11 is a schematic diagram showing the structure of a conventional internal down-converting circuit generally used in the DRAM. In FIG. 11, internal down-converting circuit VDC includes a reference voltage generating circuit RVG receiving an external power supply voltage VCE applied to an external power supply node EX and a ground voltage for generating a reference voltage Vref at a prescribed voltage level, a comparator CMP for comparing an internal power supply voltage VCI on an internal power supply line IVL with reference voltage Vref, and a current drive transistor DT constituted by a p channel MOS transistor connected between external power supply node EX and internal power supply line IVL and receiving an output signal of comparator CMP at its gate. A load circuit LC operates with the internal power supply voltage VCI on internal power supply line IVL as one operating power supply voltage. An operation of internal down-converting circuit VDC shown in FIG. 11 will now be described.
When internal power supply voltage VCI on internal power supply line IVL is higher than reference voltage Vref, the output signal of comparator CMP attains an H level and therefore conductance of current drive transistor DT is reduced, whereby current supply from external power supply node EX onto internal power supply line IVL is reduced or stopped.
Meanwhile, when internal power supply voltage VCI is lower than reference voltage Vref, the output signal of comparator CMP goes toward an L level and therefore the conductance of current drive transistor DT is increased, whereby current is supplied from external power supply node EX onto internal power supply line IVL, increasing a voltage level of internal power supply voltage VCI. This comparator CMP is normally constituted by a differential amplifier for differentially amplifying the difference between internal power supply voltage VCI and reference voltage Vref. Therefore, this current drive transistor DT supplies a current from external power supply node EX onto internal power supply line IVL in accordance with the difference between internal power supply voltage VCI and reference voltage Vref, whereby internal power supply voltage VCI is held approximately at a reference voltage Vref level.
When load circuit LC operates consuming a current on internal power supply line IVL and internal power supply voltage VCI is reduced, the output signal of comparator CMP is reduced in voltage level and current drive transistor DT supplies large current from external power supply node EX onto external power supply line IVL, restoring this internal power supply voltage VCI to the original level.
With the use of the feedback loop of current drive transistor DT and comparator CMP, internal power supply voltage VCI lower in voltage level than external power supply voltage VCE can be stably produced to operate the internal circuitry (load circuit LC).
Current drive transistor DT serves as resistance component between external power supply node EX and internal power supply line IVL. Accordingly, when load circuit LC operates consuming current on internal power supply line IVL, current drive transistor DT needs to supply a current equal to or higher than consumed current during operation of load circuit LC in order to quickly compensate for reduction in internal power supply voltage VCI resulting from the current consumption of load circuit LC to restore the internal power supply voltage to the original voltage level. Thus, the gate width W (or the ratio W/L of gate width to gate length) of current drive transistor DT is enlarged and current driving capability thereof is sufficiently increased. Therefore, the current drive transistor occupies a relatively large area.
Furthermore, when load circuit LC operates faster and consumes a larger amount of current, a current flowing in internal power supply line IVL is increased. Current consumption I is given by the expression I=f.multidot.Ce.multidot.V, wherein f indicates an operating frequency, Ce a load capacitance to be driven and V a voltage amplitude at an electrode of load capacitance Ce. Accordingly, an average current flowing in internal power supply line IVL is increased with increase in operating frequency.
In this state, if the distance between internal down-converting circuit VDC and load circuit LC is increased and the length of internal power supply line IVL therebetween is thus increased, voltage drop resulting from interconnection line resistance of internal power supply line IVL could not be ignored. This load circuit LC would operate with a voltage lower on the average than internal power supply voltage VCI as one operating power supply voltage and therefore the operational characteristic of load circuit LC cannot be assured, resulting in instability of the circuit operation.
FIG. 12 is a diagram showing another structure of a conventional internal down-converting circuit. This internal down-converting circuit VDC shown in FIG. 12 includes a level shifting circuit LS for shifting in level an internal power supply voltage VCI on an internal power supply line IVL by resistance division. An output voltage LV of level shifting circuit LS is applied to a positive input of a comparator CMP for driving a current drive transistor DT. A reference voltage Vref is applied to a negative input of comparator CMP. Current drive transistor DT and a load circuit LC have the same structure as that shown in FIG. 11.
Level shifting circuit LS includes resistive elements R1, r1, r2 and R2 connected in series between internal power supply line IVL and a ground node, and link elements F1 and F2 respectively connected in parallel with resistive elements r1 and r2 and capable of being blown off. Resistive elements R1 and R2 have a relatively large resistance value in order to reduce current consumption in this level shifting circuit LS.
When link elements F1 and F2 are in a conductive state, resistive elements r1 and r2 are short-circuited, and level shifting circuit LS serves as a resistance dividing circuit formed of resistive elements R1 and R2. At this time, a shift voltage LC given by the following expression is applied to comparator CMP. EQU LV=VCI.multidot.R2/(R1+R2)
If link element F1 is now blown off, resistive element r1 is connected in series with resistive element Rl. Accordingly, in this state, shift voltage LV is given by the following expression. EQU LV=VCI.multidot.R2/(R1+R2+rl)
More specifically, when link element F1 is blown off, shift voltage LV is reduced in level. Meanwhile, if link element F2 is blown off, resistive element r2 is connected in series with resistive element R2. In this case, shift voltage LV given by the following expression is obtained. EQU LV=VCI.multidot.(R2+r2)/(R1+R2)
In other words, when link element F2 is blown off, shift voltage LV can be increased in level. Comparator CMP compares this shift voltage LV with reference voltage Vref. Therefore, according to the structure of internal down-converting circuit VDC shown in FIG. 12, feedback control is carried out such that reference voltage Vref and shift voltage LV are at the same voltage level (through operation of comparator CMP and current drive transistor DT).
The voltage level of internal power supply voltage VCI can be adjusted by selectively blowing link elements F1 and F2 off. With the use of this level shifting circuit LS, comparator CMP can operate in the most sensitive region, the feedback loop of comparator CMP and current drive transistor DT can be improved in response characteristic, and internal power supply voltage VCI can be stably held at a prescribed voltage level.
According to the structure of internal down-converting circuit VDC, however, level shifting circuit LS includes link elements F1 and F2. Link elements Fl and F2 occupy a relatively large area (in order to prevent other elements from being short-circuited at the time of blowing off and to prevent other portions from being blown off by mistake at the time of blowing). Therefore, this level shifting circuit LS occupies a large area.
Recently, the operation speed and integration degree of the DRAM have been increasingly improved and therefore such an internal down-converting circuit need be efficiently located so as to prevent both increase in area and voltage drop.
In addition, semiconductor devices including a voltage converting circuit with a function similar to that of such an internal down-converting circuit also have similar problems with improvement in integration degree.